In the production of integrated power circuits and of power semiconductor components, it is important, during the end processes of the overall production method, to protect the semiconductor circuit arrangement that has already been formed and on which the power semiconductor component is based in the underlying semiconductor material region with respect to specific end processes and the mechanical, thermal and contamination loading associated therewith. Usually, for this purpose, after the formation of the underlying semiconductor circuit arrangement, a protection and sealing material is applied on the corresponding topmost metallization or top metallization, which material has an electrically insulating effect and protects the underlying structures against mechanical, thermal and contamination stresses.
What is problematic about this procedure is that the material layer stacks used in this case have to be provided as additional measures. On account of the higher complexity of the structures, this leads to reliability losses and to an additional process engineering outlay in the overall production method. Furthermore, the materials used in this case are associated with a cost factor which must not be underestimated.